--MYNAND.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MYNAND IS
  PORT(A:IN STD_LOGIC;
       B:IN STD_LOGIC;
       C:OUT STD_LOGIC);
END ENTITY MYNAND;

ARCHITECTURE ART1 OF MYNAND IS
  BEGIN
  C<=NOT(A AND B );
END ARCHITECTURE ART1;

ARCHITECTURE ART2 OF MYNAND IS
  BEGIN
  C<='1' WHEN (A='0') AND(B='0') ELSE
      '1' WHEN (A='0') AND(B='1') ELSE
      '1' WHEN (A='1') AND(B='0') ELSE
      '0' WHEN (A='1') AND(B='1') ELSE
      '0';
END ARCHITECTURE ART2;


CONFIGURATION CFG1 OF MYNAND IS 
  FOR ART1
  END FOR;
END CONFIGURATION CFG1;

CONFIGURATION CFG2 OF MYNAND IS 
  FOR ART2
  END FOR;
END CONFIGURATION CFG2;


